Improved on-chip communication architecture for multi-core embedded system

New tendencies envisage multi-core as a promising solution for embedded application. And the key challenge is how to improve the communication efficiency. In this paper, we propose improved on-chip communication architecture for multi-core embedded system The presented on-chip communication protocol is based on packet connected circuit (PCC), but we improve it to fit different frequency requirements of IP integrated into embedded system and support dynamic power management Besides, to improve accessing efficiency of main memory, a brand-new topology is also presented We present the prototype design base on the new architecture, which integrate 4 ARM compatible cores and 4 multiply accumulate units. Further, we design a real-time fade-in-fade-out video demo system The multi-core prototype chip runs at 90MHZ, and can accomplish real-time fade-in-fade-out processing of 4 lane video (640×480, 30fps).