Implementation of a PUF Circuit on a FPGA

Having a robust and tamper proof structure, recently proposed pyhsical unclonable functions (PUF) are considered as a promising instrument that would be used for secure key generation and storage, integrated circuit (IC) authentication and generating chip-unique signatures. We describe a delay-based PUF architecture suitable for RFID devices mostly suffer from low computational power and tiny sillicon area. In order to match these constraints, we design a mux and an arbiter based PUF circuit that is implemented on an Field Programmable Gate Array (FPGA) for experimental purposes. Based on our measurements which is extended to variable environmental conditions, we state the length of a reliable PUF circuit.