DocumentCode :
2614125
Title :
A low noise PLL based FM audio transmitter in 0.35 μm CMOS technology
Author :
Lu, Yan ; Huo, Yiming ; Tao, Tao ; Wernehag, Johan ; Sjöland, Henrik
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
fYear :
2010
fDate :
22-24 Sept. 2010
Firstpage :
202
Lastpage :
205
Abstract :
PLL (Phase Locked Loop) based frequency synthesizers are widely used in the wireless communication field. This paper puts focus on the design and implementation of a 60dB SNR (Signal to Noise Ratio) FM transmitter, which realizes direct frequency modulation of audio signal by utilizing a carrier frequency ranging from 78MHz to 108MHz, with a 100 kHz channel selection resolution. Fabricated in standard 0.35μm CMOS technology, this PLL´s core circuit takes an area of 745×700 μm2. The transmitter has a total power consumption of below 56mW for a 3V supply, and the strongest measured spur is below -50dBc.
Keywords :
CMOS integrated circuits; frequency modulation; frequency synthesizers; phase locked loops; radio transmitters; CMOS technology; FM audio transmitter; audio signal; direct frequency modulation; frequency 100 kHz; frequency 78 MHz to 108 MHz; frequency synthesizers; low noise PLL; phase locked loop; signal to noise ratio; size 0.35 mum; voltage 3 V; wireless communication; Frequency modulation; Phase locked loops; Phase noise; Radio transmitters; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-6735-8
Electronic_ISBN :
978-1-4244-6736-5
Type :
conf
DOI :
10.1109/PRIMEASIA.2010.5604927
Filename :
5604927
Link To Document :
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