A low jitter 2.125GHz serial link for optical transmission

Author

Hou, Zhongyuan ; Liu, Junhua ; Yang, Fan ; Zhang, Xin

Author_Institution

Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

146

Lastpage

149

Abstract

In this paper, a 2.125GBd 10bit Serialize/Deserialize (SERDES) system has been implemented, transmitter section and receiver section are capable of working simultaneously. A new architecture of CDR and PLL has been proposed. The same coarse loop is used in the PLL and CDR to set each digital control bits of VCO. And a pre-emphasis driver is utilized to compensate for the high frequency attenuation in channel. The measurement results show that SERDES has a RMS jitter of 28ps.

Keywords

optical links; optical phase locked loops; optical receivers; optical transmitters; timing jitter; voltage-controlled oscillators; CDR architecture; PLL architecture; RMS jitter; SERDES system; VCO; clock-data recovery; digital control bits; high frequency attenuation; low jitter serial link; optical transmission; phase-locked loop; preemphasis driver; receiver section; root mean square jitter; serialize-deserialize system; transmitter section; voltage-controlled oscillator; Clocks; Driver circuits; Jitter; Optical transmitters; Phase locked loops; Receivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604941

Filename

5604941