A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity

Author

Junlei, Zhao ; Yuan, Wang ; Zhihui, Zhao ; Song, Jia

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

85

Lastpage

88

Abstract

This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.

Keywords

CMOS integrated circuits; digital-analogue conversion; 14-bit digital-to-analog converter; CMOS process; current source array; dynamic element matching; enhanced dynamic linearity; frequency 150 MHz to 300 MHz; pipelined DEM DAC; pipelined dynamic element; power 48 mW; power supply; signal-dependent distortions; size 0.13 mum; spurious-free dynamic range; voltage 1.2 V; word length 14 bit; Arrays; CMOS integrated circuits; Encoding; Impedance; Linearity; Switches; Systematics;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604954

Filename

5604954