• DocumentCode
    2614738
  • Title

    A Study of CMOS Latch-up by Laser Scanning and Voltage Contrast Techniques

  • Author

    Wills, Kendall Scott ; Pilch, Charles J., Jr. ; Hyslop, Adin

  • Author_Institution
    Texas Instruments Inc., P.O. Box 1443, Houston, Texas 77001. (713) 274-2000
  • fYear
    1986
  • fDate
    31503
  • Firstpage
    115
  • Lastpage
    119
  • Abstract
    The susceptibility of CMOS devices to latch-up becomes of greater concern as the spacing between geometries is reduced. An advanced 1 micron CMOS device is used to examine various methods of determining where on the device latch-up might occur. Two of these methods are laser induced latch-up and scanning electron microscope (SEM) microprobe. A correlation is shown between the two methods.
  • Keywords
    CMOS technology; Circuits; Current supplies; Inverters; Laser beams; Monitoring; Power supplies; Scanning electron microscopy; System testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1986. 24th Annual
  • Conference_Location
    Anaheim, CA, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1986.362120
  • Filename
    4208651
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2614738