Towards realizing variable resolution analog to digital converters

Author

Kumar, A. Mahesh ; Veeramachaneni, Sreehari ; Srinivas, M.B.

Author_Institution

Dept. of ECE, Birla Inst. of Technol. & Sci., Hyderabad, India

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

81

Lastpage

84

Abstract

In this paper, the idea of variable resolution ADCs is proposed and implemented for all types of ADC architectures. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused sections of the ADCs to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADCs are capable of operating at 4-12 bit precision at a supply voltage of 2.5V. The sampling frequency ranges from 1.8MSPS to 1.2 GSPS that depends on ADC topologies. Variable-resolution flash, semi - flash, pipelined and SAR ADCs operating at a maximum resolution of 8-bit, 12-bit, 12bit, 10-bit respectively have been designed and verified for post layout simulations in standard 65nm CMOS technology.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; integrated circuit layout; ADC topologies; CMOS technology; exponential power reduction; linear resolution reduction; peak-detector circuit; pipelined ADC; post layout simulations; sampling frequency; semiflash ADC; size 65 nm; standby mode; variable resolution analog-digital converters; variable-resolution flash ADC; voltage 2.5 V; word length 4 bit to 12 bit; CMOS integrated circuits; Detectors; Frequency measurement; Multiplexing; Photonic band gap; Signal resolution; Voltage control; Flash; Peak Detector; Pipelined and SAR ADCs; Semi-flash;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604957

Filename

5604957