Design and implementation of an optimized FIR filter for IF GPS signal simulator

This paper presents the design and implementation of a forty-order FIR filter for IF GPS signal simulator with three algorithms: multiply and accumulate (MAC), add-and-shift scheme with CSD encoding (CSD), new common sub-expression elimination (CSE). Each scheme is analyzed in detail including design and optimization process to find the best one with the least hardware resource and power consumption. The FIR filter is coded in Verilog HDL, and then implemented using Xilinx Virtex5 FPGA and Design Compiler based on SMIC 0.18 um technology. FPGA implementation result shows that CSE consumes the least total occupied slice, with 63% and 20% reduction compared with MAC and CSD. The implementation of CSE in ASIC also proves 66% and 13% reduction in total chip area, as well as 36% and 6% dynamic power reduction compared with MAC and CSD respectively.