The relative performance enhancement of strained-Si and buried channel p-MOS as a function of lithographic and effective gate lengths

Author

Temple, M.P. ; Paul, D.J. ; Tang, Y.T. ; Waite, A.M. ; Evans, A.G.R. ; O´Neill, A.G. ; Zhang, J. ; Grasby, T. ; Parker, E.H.C.

Author_Institution

Cavendish Lab., Cambridge Univ., UK

fYear

2003

fDate

10-12 Dec. 2003

Firstpage

51

Lastpage

52

Abstract

The relative performance enhancement of strained-Si and buried channel p-MOS as a function of lithographic and effective gate lengths were investigated. Si- pMOS device results are presented from a standard 0.25 μm CMOS process. A SiGe buried channel device on a SiGe virtual substrate is also investigated. With the different diffusion constants for Si and SiGe layers part of this enchancement may be related to differences in channel length. To remove any such effects, the effective gate length (L_eff) was extracted using the shift and ratio technique and performance improvements have been compared for both lithographic gate length (L_g) and effective gate length (L_eff).

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; lithography; silicon; 0.25 micron; CMOS process; Si; SiGe; SiGe buried channel; SiGe virtual substrate; buried channel p-MOS transistor; lithography; CMOS process; Computer science; Educational institutions; Fabrication; Laboratories; MOS devices; MOSFETs; Physics; Solids;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2003 International

Print_ISBN

0-7803-8139-4

Type

conf

DOI

10.1109/ISDRS.2003.1271991

Filename

1271991