A new structure of low-power and low-voltage double-edge triggered flip-flop

In this paper a novel low-power double-edge triggered flip-flop is introduced. Double-edge triggered Flip-Flops have the data signal changes on both the clock edges. Thus, low swing clock results in lower power consumption and the data throughout are preserved. Today, the leakage current has become a critical feature for integrated circuit (IC) designers because it leads to more power consumption. So in this paper some methods have been presented to control the leakage current. The proposed circuit is simulated in 0.35 μm CMOS technology with the power supply of 1.5V. The simulations are carried out by applying HSPICE software. The results of the proposed circuit show 180nW power dissipation. The number of clock transistors decrease which in turn results in lower leakage current, hence the power consumption reduces.