DocumentCode :
2615347
Title :
A technique for selecting CMOS transistor orders
Author :
Chiang, Ting-Wei ; Chen, C. Y Roger ; Wei Yu Chen
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., Syracuse, NY
fYear :
2007
fDate :
7-10 Oct. 2007
Firstpage :
438
Lastpage :
443
Abstract :
Transistor reordering has been known to be effective in reducing delays of a circuit with nearly zero penalties. However, techniques to determine good transistor orders have not been proposed in literature. Previous work on this has to resort to running SPICE for all meaningful transistor orders and selecting a best one, which is extremely time-consuming. This paper proposes an efficient and accurate technique for determining best transistor orders without running SPICE simulations. Experimental results from SPICE3 show that the predictions are very accurate.
Keywords :
CMOS integrated circuits; delays; transistors; CMOS transistor; SPICE simulation; complementary metal-oxide semiconductor transistors; transistor reordering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2007. ICCD 2007. 25th International Conference on
Conference_Location :
Lake Tahoe, CA
ISSN :
1063-6404
Print_ISBN :
978-1-4244-1257-0
Type :
conf
DOI :
10.1109/ICCD.2007.4601936
Filename :
4601936
Link To Document :
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