Title :
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
Author :
Chen, Mingjing ; Orailoglu, Alex
Author_Institution :
CSE Dept., UC San Diego, La Jolla, CA
Abstract :
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniques with direct investigation of circuit behavior, and achieves model simplification and computational efficiency while ensuring sufficient accuracy. The circuit-level mismatch model can be used in performance characterization and yield estimation, both important in providing information for circuit reliability analysis. The proposed yield optimization technique consists of constructing and refining a yield model over the designable parameters, and ensures fast convergence to the global optimal design. The experimental results on two representative circuits confirm the efficiency and effectiveness of the proposed method.
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; network analysis; CMOS analog circuits; circuit behavior; circuit reliability analysis; circuit-level mismatch modelling; model simplification; optimal design; performance characterization; statistical technique; yield optimization; Analog circuits; CMOS analog integrated circuits; Circuit analysis; Computational efficiency; Computational modeling; Information analysis; Optimization methods; Performance analysis; Semiconductor device modeling; Yield estimation;
Conference_Titel :
Computer Design, 2007. ICCD 2007. 25th International Conference on
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
978-1-4244-1257-0
Electronic_ISBN :
1063-6404
DOI :
10.1109/ICCD.2007.4601948