Title :
A video delay line compiler
Author :
Rothan, F. ; Joanblanq, C. ; Senn, P.
Author_Institution :
CNET, Meylan, France
Abstract :
A digital delay line compiler is described. Depending on the number of bits per word, the delay required, and the operating frequency, the compiler automatically generates the layout of the block, including output and input buffers and registers for synchronization. The implementation is independent of basic cell characteristics. The architecture is described, as well as the method used for area optimization. Experimental results are discussed
Keywords :
computerised signal processing; delay lines; program compilers; software tools; video signals; area optimization; basic cell characteristics; digital delay line; input buffers; layout; operating frequency; output buffers; synchronization; video delay line compiler; CMOS process; Clocks; Delay lines; Filters; Integrated circuit interconnections; Read-write memory; Registers; Streaming media; Synchronization; Video signal processing;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.111914
