A DCT chip based on a new structured and computationally efficient DCT algorithm

Author

Duhamel, P. ; Guillemot, C. ; Carlach, J.C.

Author_Institution

CNET, Issy-les-Moulineaux, France

fYear

1990

fDate

1-3 May 1990

Firstpage

77

Abstract

A discrete cosine transform (DCT) algorithm and architecture that minimize both software and hardware costs are presented. The proposed approaches are either direct or indirect and are based on the decomposition of the DCT in three operations: permutation, fast Fourier transform, and rotation. The main characteristics of the VLSI implementation chosen for this DCT and inverse DCT algorithm are show. Its data path coupled with a twin-pages memory and its controller, which contains the microprograms of the DCT algorithm are described. The results in terms of data processing rate and silicon area are given

Keywords

VLSI; computerised picture processing; fast Fourier transforms; DCT chip; VLSI implementation; computationally efficient DCT algorithm; data path; data processing rate; decomposition; discrete cosine transform; fast Fourier transform; hardware costs; inverse DCT algorithm; microprograms; permutation; rotation; silicon area; twin-pages memory; Arithmetic; Discrete cosine transforms; Hardware; Image coding; Image communication; Image processing; Karhunen-Loeve transforms; Speech processing; Very large scale integration; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.111917

Filename

111917