Electrical environment within the silicon-on-insulator MOSFET structure

In this presentation, we present a comparative study of the SOI based transistors structures and their simulated electrical responses. Efforts are made to document how the active silicon dimension affects the internal environment of MOSFET. Shrinkage of the channel dimension nonlinearly affects the device parameters. The drain-gate coupling and the subthreshold values are also affected by the reduction of the channel length. Simulations are made on silicon-on-insulator PMOS MOSFET structure of different channel length.