Extending the performance envelope of 0.5 /spl mu/m implanted SAG-MESFET´s for supercomputer applications

The implementation, optimization, and evaluation of an ion implanted, 0.5 /spl mu/m refractory self-aligned gate GaAs MESFET process for DCFL digital ICs for supercomputer applications is described. The MESFET performance has been optimized for minimal short channel effects, ultra high performance, minimal backgating, and improved manufacturability. This device process has been coupled together with a three or four level metal interconnect process for producing 1 GHz clock rate LSI to VLSI digital computer ICs. The interconnect process makes use of up to four levels of CVD tungsten via fill for planarity throughout the interconnect process. This process yields typical propagation delays of 25 pS for a 2/4 /spl mu/m inverter with unity fanout. Four input NOR gates with a fanout of four have a typical delay of 65 pS. Moreover, a four input NOR buffer driving a fanout of seven through 500 /spl mu/m of minimum geometry metal has a delay of 63 pS. This delay increases to 93 pS when the metal length is increased to 1500 /spl mu/m. This process is being used to produce 5 to 10 K gate digital circuits for the 1 GHz clock rate Cray-4 supercomputer. This work has resulted in a manufacturing process which produces devices and circuits with world class performance.<>