Title :
Implementation of a deep space receiver on 350 K gate GaAs gate arrays
Author :
Burke, G.R. ; Chow, T.W. ; Graham, J.S. ; Kowalski, J.E. ; Whitaker, W.D. ; Johnson, R.A.
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
Abstract :
A set of three GaAs ASICs has been designed. Together they form part of the Block V Digital Receiver. Each ASIC contains approximately 150 K-170 K used gates. The authors describe the design methodology for the GaAs ASICs, which ensures successful timing, testability, and functionality.<>
Keywords :
III-V semiconductors; application specific integrated circuits; design for testability; digital signal processing chips; direct coupled FET logic; emitter-coupled logic; field effect logic circuits; gallium arsenide; logic CAD; logic arrays; logic partitioning; logic testing; receivers; space communication links; timing; transistor-transistor logic; ASICs; ATPG; Block V Digital Receiver; DCFL; ECL; GaAs gate arrays; III-V semiconductor; Jetcar; Jetsub; Jetsym; TTL; Vitesse gates; deep space receiver; design methodology; functionality; testability; timing; Application specific integrated circuits; CMOS technology; Demodulation; Gallium arsenide; Laboratories; Oscillators; Propulsion; Routing; Space technology; Tracking loops;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394481
