3-D simulation of strained Si/SiGe heterojunction FinFETs

The 3D structure and simulation of strained Si/SiGe FinFETs is proposed in this paper. A channel doping of 10¹⁶ cm^-3, dual polysilicon gate 1.5 nm gate oxide, abrupt source/drain-to-channel junctions, and a Si_0.8Ge_0.2 body with fixed 5 nm surrounding Si are used in the 3D simulation. Strained Si/SiGe device at the threshold voltage (V_T) yields a better gate control, smaller roll-off characteristics, smaller subthreshold swing, and significant g_m enhancement. This novel strained Si/SiGe FinFET with the enhanced carrier mobility and heterojunction confinement is demonstrated with greatly improved performance for NMOS by 3-D simulation.