Title :
A 25 k-gate BDCFL G/A with a differential push-pull ECL I/O
Author :
Kaneko, Y. ; Shimizu, H. ; Nagata, K. ; Koyanagi, M. ; Okamoto, M. ; Suzuki, M. ; Yokokawa, S. ; Shimizu, Shogo ; Maejima, T. ; Wada, J. ; Kawada, H. ; Ueno, S. ; Minamizawa, M. ; Yaegashi, I.
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
The authors develop a 25 k-gate array with 0.8-/spl mu/m buried p-layer MESFET, three-level gold-based interconnects, and Au bump technology. They use differential push-pull circuits for the ECL interface circuits to obtain a sufficient margin, a low-voltage (-1.6 V) power supply for the internal gates to reduce the power consumption, and -2.0 V for the I/O circuits. The basic cell array combines DCFL and ECL compatible buffered DCFL gates (BDCFL). The basic delay times are 45 ps for 0.75 mW DCFL and 60 ps for 1.2 mW BDCFL gates. The gate array chip size is 10.7/spl times/10/7 mm, and contains 24,320 three-input BDCFL internal gates. The authors also use 80 /spl mu/m TAB to reduce the package delay time and simultaneous switching output noise. They use the array in a vector parallel processor which has a peak performance of 355 GFLOPS.<>
Keywords :
III-V semiconductors; MESFET integrated circuits; application specific integrated circuits; buffer circuits; differential amplifiers; direct coupled FET logic; emitter-coupled logic; field effect logic circuits; gallium arsenide; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; logic arrays; parallel architectures; tape automated bonding; vector processor systems; -1.6 V; -2 V; 0.75 mW; 0.8 micron; 1.2 mW; 355 GFLOPS; 45 ps; 60 ps; Au bump technology; BDCFL; ECL I/O; ECL compatible; GaAs; III-V semiconductor; TAB; WSi; buffered DCFL gates; buried p-layer MESFET; circuit design; circuit fabrication; delay times; differential push-pull circuits; low voltage power supply; self-aligned refractory gate; vector parallel processor; Circuit synthesis; Delay lines; Energy consumption; Gold; Integrated circuit interconnections; MESFETs; Packaging; Power dissipation; Power supplies; Voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1393-3
DOI :
10.1109/GAAS.1993.394483
