HBT gate array for 5 GHz ASICs

Author

Yinger, S. ; Lee, F. ; Huang, R. ; Schneider, K. ; Wang, E. ; Smith, K. ; Penugonda, M. ; Jacobs, S. ; Carter, T.

Author_Institution

Rockwell Int. Corp., Newbury Park, CA, USA

fYear

1993

fDate

10-13 Oct. 1993

Firstpage

87

Lastpage

90

Abstract

A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. Chip size is 2.2 mm /spl times/ 2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 watts. The top level gate delay is 55 ps for a fanout of one and 60 fF load.<>

Keywords

III-V semiconductors; aluminium compounds; application specific integrated circuits; bipolar logic circuits; circuit layout CAD; current-mode logic; gallium arsenide; integrated circuit layout; logic CAD; logic arrays; multivalued logic circuits; very high speed integrated circuits; 1 to 3 W; 3-level logic; 5 GHz; 5 Gbit/s; 55 ps; AlGaAs-GaAs; CAD tools; CML; III-V semiconductor; automatic placement; cell library; complex logic functions; high speed ASIC; high speed HBT gate array; power dissipation; top level gate delay; Application specific integrated circuits; Circuit synthesis; Delay; Heterojunction bipolar transistors; Logic arrays; Logic design; Logic gates; Power dissipation; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1993. Technical Digest 1993., 15th Annual

Conference_Location

San Jose, CA, USA

Print_ISBN

0-7803-1393-3

Type

conf

DOI

10.1109/GAAS.1993.394493

Filename

394493