Title :
A multiple row-based layout generator for CMOS cells
Author :
Lakhani, Gopal ; Rao, Satish
Author_Institution :
Dept. of Comput. Sci., Texas Tech. Univ., Lubbock, TX, USA
Abstract :
An implementation of a layout generator which follows a multi-row-based layout style is presented. By considering multiple rows in the same cell, it is possible to incorporate the complexity of the inter-row routing in the placement phase. The cell generator is more suitable for circuits that contain both structured and random logic. It is targeted for use in the automatic generation of custom cell libraries. Unlike previous cell generators which consider only the width optimization, the authors´ cell generator tries to minimize the layout area by explicitly considering both dimensions of the layout in the cost function
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; logic CAD; CMOS cells; SUN-3 workstation; automatic generation; cost function; custom cell libraries; logic gates; multiple row-based layout generator; net routing; placement phase; random logic; structured logic; width optimization; Computer science; Cost function; Libraries; Logic circuits; MOS devices; MOSFETs; Minimization; Routing; Strips; Variable structure systems;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.111941
