PASIC: A processor-A/D converter-sensor integrated circuit

Author

Chen, K. ; Afghani, M. ; Danielsson, P.E. ; Svensson, C.

Author_Institution

Linkoping Univ., Sweden

fYear

1990

fDate

1-3 May 1990

Firstpage

1705

Abstract

The design of an integrated smart sensor called PASIC is described. The basic idea is to integrate a 2-D image-sensor array with a linear A/D (analog-to-digital) converter array and a linear processor array in a single chip. The current version of PASIC contains 128 parallel processors with a 128×128-b memory, 128 8-b A/D converters, and a 128×128 photo sensor array. Two 128×8 bidirectional shift registers are used for communication between processor elements and I/O (input/output). A memory-bus organized architecture is used, having been proven as an efficient VLSI architecture for a SIMD (single instruction, multiple data) bit-serial processor array

Keywords

CMOS integrated circuits; VLSI; analogue-digital conversion; computer vision; image sensors; 2D image sensor array; 8 bit; CMOS technology; PASIC; SIMD bit serial processor array; VLSI; VLSI architecture; analogue to digital convertor array; bidirectional shift registers; integrated smart sensor design; linear processor array; memory-bus organized architecture; photo sensor array; processor-A/D converter-sensor integrated circuit; single instruction multiple data; Bidirectional control; Image converters; Image processing; Image sensors; Intelligent sensors; Robot vision systems; Sensor arrays; Shift registers; Spatial resolution; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.111947

Filename

111947