DocumentCode :
2616570
Title :
Error analysis and digital correction algorithms for pipelined A/D converters
Author :
Hadidi, Kh ; Temes, G.C. ; Martin, K.W.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
fYear :
1990
fDate :
1-3 May 1990
Firstpage :
1709
Abstract :
The conversion error of a pipelined A/D (analog-to-digital) converter using inaccurate comparators is analyzed. It is shown that the error can be compensated using simple analog circuitry combined with some digital logic. The resulting system is especially useful for fast converters in which accurate comparators would require a large chip area and large DC power
Keywords :
CMOS integrated circuits; analogue-digital conversion; error correction; pipeline processing; CMOS differential comparators; DC power; analog circuitry; analogue to digital convertor; conversion error; digital correction algorithms; digital logic; error analysis; inaccurate comparators; pipelined A/D converters; Circuit noise; Digital circuits; Error analysis; Error correction; Hysteresis; Laboratories; Latches; Logic; Pipelines; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
Type :
conf
DOI :
10.1109/ISCAS.1990.111950
Filename :
111950
Link To Document :
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