Test sequence generation of Random Single Input Change based on counter

Source of power consumption for digital CMOS is analyzed and low power consumption technology of BIST for COMS VLSI is summarized in this paper. In order to reduce the internal switching activity rate of the circuit -under-test (CUT), we can recombine testing vector to raise the correlation between testing vector, an approach test pattern generation construction based on the Random Single Input Change (RSIC) test theory is proposed, which optimize the switching activity of circuit-under test and then result in decrease of test power consumption, it is suitable for BIST of digital VLSI especially.