DocumentCode
2616960
Title
Finite-difference time-domain modeling of currents in multi-layered computer chip packages
Author
Becker, W. ; Chebolu, S. ; Mittra, R.
Author_Institution
IBM Corp., Kingston, NY, USA
fYear
1993
fDate
20-22 Oct 1993
Firstpage
181
Lastpage
184
Abstract
Finite difference time domain (FDTD) modeling of the currents in the power leads of a computer chip package is presented. The limits of the quasi-static solution are investigated, and techniques for efficient analysis of these complex structures are discussed
Keywords
circuit analysis computing; finite difference time-domain analysis; integrated circuit packaging; FDTD modelling; circuit simulator; finite difference time domain modelling; multilayered computer chip package; power leads; quasistatic solution; Computer networks; Electromagnetic analysis; Finite difference methods; Frequency response; Geometry; High performance computing; Packaging; Power engineering computing; Time domain analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1993
Conference_Location
Monterey, CA
Print_ISBN
0-7803-1427-1
Type
conf
DOI
10.1109/EPEP.1993.394559
Filename
394559
Link To Document