The method of increasing of the voltage gain of the classical differential stages with passive resistive load

The new architecture of the differential stages (DS), that provides the increase of the voltage gain on 1 or 2 orders without using of the classical active loads (current mirrors) on p-n-p transistors is considered. The recommended application field is analog and analog-to-digital circuits with the low supply voltage. The effect of increasing of the gain of DS at relatively low-ohmic resistors of the collector load (R1=R2=600÷800 Ohms) is provided due to the introduction of a special scheme of their cancellation. The increase of the gain up to 40÷70 dB requires the mismatch of the rating values of the resistors R1, R2 in the range of 5÷10%. The results of the computer simulation of DS for the bipolar technological process HJV Zarlink Semiconductor are shown.