Minimum-Congestion Placement for Y-interconnects: Some studies and observations

Y-interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0deg, 60deg, and 120deg. Though X-interconnects are fast replacing the traditional Manhattan (M) interconnects, the very recently proposed Y-interconnects have been observed to possess certain key advantages, Y-interconnects tend to consume less routing resources than M-interconnects. Unlike the X-interconnect architectures, Y-interconnect architectures support regular routing grid. This is indeed very important for simplifying manufacturing processes and applying the routing and design rule checking algorithms. Several efficient Y-routing algorithms have been proposed in literature. However, to the best of our knowledge, not much have been reported so far in designing algorithms for Y-interconnect-based VLSI module placement and its effects on the congestion or wire-lengths. In this paper, in an attempt to fill the gap in the existing literature, we propose a novel simulated-annealing-based placement technique for mixed-sized cells which tries to reduce the congestion for Y-interconnects. The proposed method attempts to reduce the congestion, and observes the corresponding changes in the estimated lengths of the Y-interconnects. It has been implemented in Linux environment and experiments performed with randomly generated instances, and some well-known benchmarks. The wirelength estimates for the Y-interconnects, and Manhattan interconnects for the same placement instances are compared. Results obtained are quite encouraging. The experimental results for a specific number of iterations and cooling schedule show improvements in congestion in most of the cases