Title :
Multilayer interconnection model for BiCMOS SRAMs
Author :
Rayapati, Venkatapathi N. ; Kaminska, Bozena
Author_Institution :
Dept. of Electr. Eng., Montreal Univ., Que., Canada
Abstract :
A multi-layer interconnect model for mega bit BiCMOS SRAMs is developed. The model is based on interconnection resistance, capacitance, and inductance associated with the BiCMOS SRAM cell. The interconnect effect on SRAM device performance parameters, propagation delay, speed, power consumption, and noise parameters are analyzed. A case study is presented for 1-Mb BiCMOS SRAM chip interconnection problems
Keywords :
BiCMOS memory circuits; SRAM chips; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; 1 Mbit; BiCMOS SRAM cell; BiCMOS SRAM chip interconnection; capacitance; device performance parameters; interconnection resistance; multilayer interconnection model; noise parameters; power consumption; propagation delay; BiCMOS integrated circuits; Electric resistance; Energy consumption; Inductance; Nonhomogeneous media; Parasitic capacitance; Performance analysis; Propagation delay; Random access memory; SRAM chips;
Conference_Titel :
Electrical Performance of Electronic Packaging, 1993
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-1427-1
DOI :
10.1109/EPEP.1993.394576
