Title :
A hardware implementation of the JVT Rate Control for H.264
Author :
Kefalas, Nikolaos ; Theodoridis, George
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Patras, Patras, Greece
Abstract :
The Rate Control is included in each video encoder and exhibits high computational complexity. In order to meet hard real time requirements, a hardware implementation is required. In this paper, a high-performance hardware architecture is proposed. Specifically the RC algorithm included in the JM software has been modified at the Basic Unit level to allow an efficient implementation. The modified RC has comparable image quality while achieving the requirements for UHD resolutions.
Keywords :
computational complexity; image resolution; video coding; JM software; JVT rate control; UHD resolution; basic unit level; computational complexity; hardware implementation; high-performance hardware architecture; image quality; modified RC algorithm; video encoder; Algorithm design and analysis; Computer architecture; Engines; Hardware; IP networks; Pipelines; Software algorithms; H.264; JM; hardware implementation; pipeline; rate control;
Conference_Titel :
Telecommunications Forum Telfor (TELFOR), 2014 22nd
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-6190-0
DOI :
10.1109/TELFOR.2014.7034512
