• DocumentCode
    2617465
  • Title

    Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks

  • Author

    Taghavi, Taraneh ; Sarrafzadeh, Majid

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA
  • fYear
    2007
  • fDate
    9-11 March 2007
  • Firstpage
    213
  • Lastpage
    218
  • Abstract
    With the increasing sophistication of circuits and specifically in the presence of IP blocks, new estimation methods are needed in the design flow of large-scale circuits. Up to now, a number of post-placement congestion estimation techniques in the presence of IP blocks have been presented. The authors propose a novel stochastic pre-placement approach for concurrent congestion and wirelength estimation using the Rent´s exponent of the circuit. The experiments illustrate that the proposed method can quickly and accurately estimate wirelength and congestion. Simulation results show that the average error of the proposed wirelength estimation technique is less than 7%. Moreover, it is shown that in presence of IP blocks using a congestion removal technique based on our congestion estimation method results in 12.8% decrease in overflow on average
  • Keywords
    VLSI; industrial property; integrated circuit design; network routing; IP blocks; Rent exponent; congestion estimation; congestion removal; hierarchical placement; large-scale circuits; network routing; wirelength estimation; Algorithm design and analysis; Circuit simulation; Computer science; Equations; Gaussian distribution; Large-scale systems; Logic; Routing; Stochastic processes; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
  • Conference_Location
    Porto Alegre
  • Print_ISBN
    0-7695-2896-1
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2007.48
  • Filename
    4208918