• DocumentCode
    2617479
  • Title

    An Efficient Analytical Approach to Path-Based Buffer Insertion

  • Author

    Kheirabadi, Hamid Reza ; Zamani, Morteza Saheb ; Saeedi, Mehdi

  • Author_Institution
    Dept. of IT & Comput. Eng., Amirkabir Univ. of Technol., Tehran
  • fYear
    2007
  • fDate
    9-11 March 2007
  • Firstpage
    219
  • Lastpage
    224
  • Abstract
    In this paper, an analytical approach to path-based buffer insertion is presented. Using the formulation, various objective functions in buffer costs can be minimized. Previous path-based buffer insertion algorithms either employ inaccurate delay estimation leading to an infeasible solution or process each path independently that may not use the effects of shared nets in paths and therefore, cannot optimize buffer cost efficiently. The approach was tested using ISCAS benchmarks. Experimental results show that our approach can satisfy timing constraints with a 46.69% reduction in the number of buffers. Reducing the number of the buffers can simultaneously reduce physical synthesis complexity as well as power consumption.
  • Keywords
    VLSI; buffer circuits; delays; integrated circuit design; timing; VLSI; buffer insertion; delay estimation; integrated circuit design; timing constraints; Benchmark testing; Cost function; Delay estimation; Energy consumption; Integrated circuit interconnections; Libraries; Quadratic programming; Timing; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
  • Conference_Location
    Porto Alegre
  • Print_ISBN
    0-7695-2896-1
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2007.23
  • Filename
    4208919