DocumentCode :
2617491
Title :
Integrated Gate and Wire Sizing at Post Layout Level
Author :
Hanchate, Narender ; Ranganathan, Nagarajan
Author_Institution :
Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL
fYear :
2007
fDate :
9-11 March 2007
Firstpage :
225
Lastpage :
232
Abstract :
The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting
Keywords :
delays; game theory; integrated circuit design; integrated circuit interconnections; integrated circuit noise; network routing; Cadence place and route tools; aggressor gates; crosstalk noise; game theory; integrated sizing algorithm; interconnect delay; wire sizing; Computer science; Constraint theory; Crosstalk; Delay; Design optimization; Game theory; Iterative algorithms; Lagrangian functions; Solid modeling; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
Type :
conf
DOI :
10.1109/ISVLSI.2007.59
Filename :
4208920
Link To Document :
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