DocumentCode
2617522
Title
CMP-aware Maze Routing Algorithm for Yield Enhancement
Author
Yao, Hailong ; Cai, Yici ; Hong, Xianlong
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear
2007
fDate
9-11 March 2007
Firstpage
239
Lastpage
244
Abstract
Chemical-mechanical polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This paper proposes a novel optimal maze routing (OMR) algorithm which optimizes the layout uniformity as well as other routing objectives. The presented routing algorithm is optimal in the sense that it can find routing solutions for nets with minimum wire length, minimum number of vias and minimized layout uniformity-related cost. Experimental results show that compared with a previous routing algorithm, OMR can reduce the total number of vias by up to 24%. Except for the great improvement considering wire length and vias, the proposed routing algorithm also contributes a lot to minimizing the pattern density variation. Since current area fill methods are mostly based on fixed-dissection regime which cannot find the optimal filling solution for all possible floating windows, the proposed routing algorithm makes a good complement.
Keywords
VLSI; chemical mechanical polishing; integrated circuit layout; integrated circuit yield; nanoelectronics; network routing; chemical mechanical polishing; floating windows; integrated circuit layout; nanometer VLSI manufacturing; optimal maze routing; pattern density variation; Chemical processes; Cost function; Filling; Manufacturing processes; Ordinary magnetoresistance; Routing; Runtime; Tiles; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location
Porto Alegre
Print_ISBN
0-7695-2896-1
Type
conf
DOI
10.1109/ISVLSI.2007.30
Filename
4208922
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