Electrical packaging requirements for low voltage ICs-3.3 V High Performance CMOS devices as a case study

Summary form only given, as follows. High performance CMOS device technology for 5 V and 3.3 V operations is discussed. Off-chip package delays and simultaneous switching noise (SSN) are selected as metrics to evaluate the impact due to packaging. Devices are housed in quad flat packages (QFPs) and pin grid array (PGAs) packages. With 3.3 V supply, to have a computationally comparable system, device sizes need to be changed to obtain similar current drive. Devices are scaled to achieve similar and enhanced performance for reduced supply voltage. Maintaining computational throughput (CTP) introduces comparable noise levels for 5 V and 3.3 V operations. This increases the probability of false switching in 3.3 V operation. Noise levels for lesser, comparable, and faster CTP 3.3-V packaged devices are given. False switching for 3.3 V operation is analyzed using receiver dynamic noise immunity (DNI). Trends in overall noise-to-signal ratio for further reduced supply voltages are given