Title :
Low-power device design of fully-depleted SOI MOSFETs
Author :
Hiramoto, Toshiro ; Nagumo, Toshiaki ; Ohtou, Tetsu
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
Abstract :
A new device concept for variable γ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient γ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.
Keywords :
power MOSFET; power consumption; semiconductor device models; silicon-on-insulator; BOX; VLSI; buried oxide; characteristic fluctuations; fully depleted SOI MOSFET; low aspect-ratio channel; low-power device design; performance degradation; semiplanar 3D gate SOI MOSFET; short effect immunity; standby power consumption; substrate depletion layer capacitance; three dimensional gate structure; variable γ FD SOI MOSFET; Degradation; Energy consumption; Fluctuations; MOSFETs; Parasitic capacitance; Physics; Solid state circuits; Threshold voltage; Very large scale integration;
Conference_Titel :
Semiconductor Device Research Symposium, 2003 International
Print_ISBN :
0-7803-8139-4
DOI :
10.1109/ISDRS.2003.1272148
