Title :
Partial Product Reduction for Parallel Cubing
Author :
Stine, James E. ; Blank, Jeff M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK
Abstract :
A new technique for computing the cube of an operand of any length is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is faster than previously proposed methods that compute the cube of an operand in parallel with the disadvantage that more counters are utilized to perform partial product reduction. Cubing circuits using the proposed techniques are implemented with several operand lengths and analyzed with regard to area consumption and latency. Results are shown for several designs in AMI C5N 0.6 mum technology
Keywords :
digital arithmetic; logic design; 0.6 micron; AMI C5N technology; counters; cubing circuits; operand cube computing; parallel cubing; partial product reduction; Ambient intelligence; Concurrent computing; Counting circuits; Cryptography; Delay; Function approximation; Hardware; Parallel processing; Signal processing; Table lookup;
Conference_Titel :
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location :
Porto Alegre
Print_ISBN :
0-7695-2896-1
DOI :
10.1109/ISVLSI.2007.78
