DocumentCode
2617940
Title
Investigating Simple Low Latency Reliable Multiported Register Files
Author
Ricketts, Andrew J. ; Mutyam, Madhu ; Vijaykrishnan, N. ; Irwin, Mary Jane
Author_Institution
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
fYear
2007
fDate
9-11 March 2007
Firstpage
375
Lastpage
382
Abstract
Multiport register files are a key component in the design and operation of high performance microprocessors. Due to the frequency of accesses of these register files per clock cycle errors manifested here can potentially spread rapidly. This can seriously compromise the validity of data and even system reliability. Errors may be caused from any number of possible sources including radiation induced soft errors, read or write errors, and permanent device errors. This work focuses on combating errors that affect a stored entry in a register file, but our techniques can often also detect and recover from many other potential sources of errors. Up to 4 bit errors are detectable with 6.25% storage overhead over an unprotected register file. The recovery for most types of errors requires in the order of a few nanoseconds and requires 4% less energy than a monolithic register file with comparable characteristics but no error protection
Keywords
error detection; multiport networks; shift registers; bit errors; monolithic register file; multiport register files; unprotected register file; Clocks; Computer science; Crosstalk; Delay; Design engineering; Frequency; Information technology; Microprocessors; Registers; Reliability engineering;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location
Porto Alegre
Print_ISBN
0-7695-2896-1
Type
conf
DOI
10.1109/ISVLSI.2007.62
Filename
4208943
Link To Document