• DocumentCode
    2618052
  • Title

    Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets

  • Author

    Najibi, M. ; Niknahad, M. ; Pedram, H.

  • Author_Institution
    Comput. Eng. Dept., Amirkabir Univ. of Technol., Tehran
  • fYear
    2007
  • fDate
    9-11 March 2007
  • Firstpage
    422
  • Lastpage
    427
  • Abstract
    A framework for evaluating the performance of asynchronous systems is presented. Due to the dependencies among highly concurrent events performance evaluation of asynchronous circuits is a challenging process. The presented performance model is a probabilistic timed Petri-net (PTPN) with possible choice places to capture the conditional behavior of the system. The proposed framework takes advantage of both static and dynamic analysis to provide precisely enough results in an acceptable time. No data manipulation is done during the simulation phase of the performance evaluation method which leads to very fast simulation. Our proposed performance estimation scheme is faster than usual post-synthesis simulation by an order of 10, while the estimated performance resides in a boundary of 3% of the total imprecision.
  • Keywords
    Petri nets; asynchronous circuits; performance evaluation; asynchronous circuits; dynamic analysis; performance estimation scheme; performance evaluation method; post-synthesis simulation; probabilistic timed Petri nets; static analysis; Asynchronous circuits; Circuit synthesis; Clocks; Computational modeling; Delay; Hardware design languages; Integrated circuit interconnections; Performance analysis; Petri nets; Signal synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
  • Conference_Location
    Porto Alegre
  • Print_ISBN
    0-7695-2896-1
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2007.80
  • Filename
    4208950