Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder

Author

Zatt, Bruno ; Azevedo, Arnaldo ; Agostini, Luciano ; Susin, Altamiro ; Bampi, Sergio

Author_Institution

Microelectron. Group, UFRGS, Porto Alegre

fYear

2007

fDate

9-11 March 2007

Firstpage

445

Lastpage

446

Abstract

This paper presents a motion compensation memory hierarchy for an H.264/AVC decoder with support to bi-predictive frames. The designed memory hierarchy reduces the memory bandwidth through the use of a three-dimensional cache and through the use of extra memory saving techniques. The cache size parameters were determined through the evaluation of simulation results from real video sequences. The designed memory hierarchy provides, in average, a 60% of bandwidth reduction. The architecture was designed in VHDL and synthesized for a Xilinx Virtex-II PRO FPGA

Keywords

cache storage; codecs; field programmable gate arrays; hardware description languages; memory architecture; motion compensation; 3D cache; FPGA; H.264/AVC decoder; VHDL; bi-predictive motion compensation; cache size parameters; memory bandwidth; memory saving techniques; motion compensation memory hierarchy; Automatic voltage control; Bandwidth; Chromium; Decoding; IEC standards; ISO standards; Motion compensation; Throughput; Video coding; Video sequences;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Conference_Location

Porto Alegre

Print_ISBN

0-7695-2896-1

Type

conf

DOI

10.1109/ISVLSI.2007.64

Filename

4208954