A new common subexpression elimination algorithm with application in composite field AES S-box

Common subexpression elimination (CSE) is a critical procedure in many multiplierless implementation of DSP algorithms. The aim of CSE is dual-pronged: 1) to reduce the number of logic operators used and 2) to minimize the logic depth (critical path) of the DSP algorithm implemented in VLSI. In this work, a novel hybrid heuristic CSE algorithm that combines greedy algorithm and exhaustive search to select the best set of common subexpressions is proposed. The proposed algorithm aims at promoting area optimization in linear transformations with binary matrix multiplication. The efficiency of the proposed algorithm is demonstrated through a case study in constructing a composite field implementation of Advanced Encryption Standard (AES). Experimental results has shown that the proposed algorithm achieves an average area reduction of 44.09% as well as an average logic depth minimization of 47.55%.