DocumentCode
2618259
Title
Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload
Author
Carvalho, Elyson ; Calazans, Ney ; Moraes, Fernando
Author_Institution
FACIN, Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre
fYear
2007
fDate
9-11 March 2007
Firstpage
459
Lastpage
460
Abstract
This work investigates the performance of different mapping algorithms in NoC-based MPSoCs with dynamic workload. The main cost function in mapping algorithms is to optimize the occupation of the NoC links. It is possible to achieve performance gains if the mapping algorithm is able to minimize NoC congestion.
Keywords
logic design; network-on-chip; system-on-chip; NoC congestion; NoC-based MPSoC; congestion-aware task mapping; dynamic workload; multiprocessor system-on-chip; network-on-chip; Communication system control; Cost function; Equations; Hardware; Network-on-a-chip; Neural networks; Performance gain; Reconfigurable logic; Resource management; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location
Porto Alegre
Print_ISBN
0-7695-2896-1
Type
conf
DOI
10.1109/ISVLSI.2007.32
Filename
4208961
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