MDCsim-a fast timing simulation program for MOS digital circuits

An approach for circuit-level timing simulation of MOS logic networks is proposed. A very fast switch-level simulation is carried out to supply a good initial guess for the timing simulator, which requires only one Gauss-Seidel iteration to solve the electrical node equations. A transistor model which utilizes a linear equation to approximate the root function in the Shichman-Hodges model is used. As a result, the electrical node equations can be solved directly with the square equation formula instead of using many Newton-Raphson iterations. Results show that, because of the good initial guess and the simplification of the nonlinear node equation, even circuits with strongly coupled logic feedback loops can be analyzed very efficiently with almost the same accuracy provided by SPICE