DocumentCode
2618584
Title
Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies
Author
Moalemi, Vahid ; Afzali-Kusha, Ali
Author_Institution
Sch. of Electr. & Comput. Eng., Tehran Univ.
fYear
2007
fDate
9-11 March 2007
Firstpage
514
Lastpage
515
Abstract
In this paper, subthreshold 1-bit full adder cells in sub-100 nm technologies are investigated. The analysis is performed using fourteen different full adder cells operating in subthreshold region by decomposing them into smaller blocks. Both individual blocks and the complete full adder cells are simulated. The study, which is carried out for 65nm and 90nm standard CMOS technologies, includes power, delay, and power delay product as functions of supply voltage, frequency, size, and technology. In addition, for both technologies, the minimum required supply voltage for different circuits, are determined
Keywords
CMOS logic circuits; adders; logic design; nanotechnology; 1 bit; 100 nm; 65 nm; 90 nm; CMOS technologies; full adder cells; power delay product; subthreshold region; Adders; CMOS technology; Capacitance; Circuit simulation; Delay; Energy consumption; Frequency; Performance analysis; Threshold voltage; Wrist;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on
Conference_Location
Porto Alegre
Print_ISBN
0-7695-2896-1
Type
conf
DOI
10.1109/ISVLSI.2007.93
Filename
4208977
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