A 5 ns 1 Mb BiCMOS SRAM with ECL I/O interface

Author

Takada, Masahide ; Nakamura, Kazuyuki ; Takeshima, Toshiaki ; FURUTA, Kouichirou ; Yamazaki, Tohru ; Imai, Koichi ; Ohi, Kiyotaka Imai Susumu ; Fukuda, Yumi ; Minato, Yukio ; Kimoto, Hisamitsu

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1990

fDate

1-3 May 1990

Firstpage

1995

Abstract

A high-speed X-address decoding scheme with wired-OR bipolar predecoders and partial decoding level converters is presented. In addition, a sensing scheme with small signal voltage swing (particularly for read bus lines) is described. These two high-speed schemes and a double-level polysilicon layer, double-level metal layer, 0.8- mu m BiCMOS process technology were used to implement a 5-ns address access time, 1-W power dissipation, and 1-Mb emitter-coupled logic input/output (I/O) interface SRAM (static random-access memory).<>

Keywords

BIMOS integrated circuits; SRAM chips; decoding; emitter-coupled logic; 0.8 micron; 1 Mbit; 1 W; 5 ns; BiCMOS SRAM; BiCMOS process technology; ECL I/O interface; Si layer; address access time; double-level metal layer; double-level polysilicon layer; high-speed X-address decoding scheme; partial decoding level converters; power dissipation; read bus lines; sensing scheme; static random-access memory; wired-OR bipolar predecoders; BiCMOS integrated circuits; Decoding; Delay effects; Differential amplifiers; Driver circuits; Large-scale systems; National electric code; Random access memory; Silicon; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA, USA

Type

conf

DOI

10.1109/ISCAS.1990.112121

Filename

112121