CMOS digital adaptive decision feedback equalizer chip for multilevel QAM digital radio modems

The design of a complex-valued single-chip digital adaptive decision feedback equalizer for 256 quadrature amplitude modulation (QAM) radio modems is described. The chip contains 62000 transistors on a silicon area of 75 mm² and is designed for operation at frequencies of up to 70 MHz, in a 1.5-μm CMOS technology. In high-speed applications clocking is a very critical issue in the systems design. The high operating frequency is achieved by performing a proper nonuniform redistribution of the delays over the data paths. The limitations are discussed for such a nonuniform distribution with respect to a maximum operating frequency required to be independent of the clocking scheme (i.e. nonoverlap of complementary two-phase clock system, etc.)