Monolithic GaAs programmable parallel-to-serial and serial-to-parallel converters

GaAs monolithic parallel-to-serial (P/S) and serial-to-parallel (S/P) converters which provide significant improvements in speed and power performance over previously reported devices are described. The converters are designed with an architecture that provides automatic frame synchronization, simple cascadability, and low power dissipation. Each chip provides an output clock in phase with the output data to facilitate postprocessing. The P/S and S/P chips operate at data rates of 1.9 Gb/s and 2.1 Gb/s, respectively, and each requires less than 120 mW of power. The chips are implemented with DCFL using a version of ITT´s multifunction self-aligned gate fabrication process