DocumentCode :
2620016
Title :
Results of an on pixel sparsification architecture in a MAPS test chip in STM 130nm technology
Author :
Spiriti, E. ; Mlynarczyk, J.
Author_Institution :
National Institute of Nuclear Physics, Rome Tre, 00146 Italy
fYear :
2008
fDate :
19-25 Oct. 2008
Firstpage :
1118
Lastpage :
1122
Abstract :
The paper presents a new approach for sparsification using only NMOS transistors to implement the on pixel signal processing. The use of PMOS transistors would create competing N-well that would drain part of the signal charge. The architecture that, using about seventy transistors, implements: correlated double sampling, signal discrimination and analog information storing on each pixel is briefly described. The test chip, submitted as a multiproject run in the STMicroelectronics 130nm technology, is described. The first results of the chip characterization with radioactive sources, some preliminary test beam data and the threshold dispersion measurements for the digital part of the sparsified architecture is presented.
Keywords :
Circuits; Diodes; Electrons; Energy resolution; MOSFETs; Noise level; Signal processing; Signal sampling; Telephony; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE
Conference_Location :
Dresden, Germany
ISSN :
1095-7863
Print_ISBN :
978-1-4244-2714-7
Electronic_ISBN :
1095-7863
Type :
conf
DOI :
10.1109/NSSMIC.2008.4774596
Filename :
4774596
Link To Document :
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