2.4 A 25Gb/s 5.8mW CMOS equalizer

The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer, and the front-end equalizer. The use of charge-steering techniques has shown promise for the low-power implementation of the first two functions [1]. This paper introduces a half-rate 25Gb/s equalizer employing charge steering and achieving an efficiency of 0.232mW/Gb/s.