2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS

Author

Rui Bai ; Palermo, Samuel ; Chiang, Patrick Yin

Author_Institution

Oregon State Univ., Corvallis, OR, USA

fYear

2014

fDate

9-13 Feb. 2014

Firstpage

46

Lastpage

47

Abstract

In this work, a DFE is presented that is designed specifically to operate at low V_DD and scale well in energy-efficiency. To achieve this goal, the following innovations are introduced: 1) fast and energy-efficient charge-based latch and sample-and-hold (S/H) topologies; 2) a CMOS-clocked quarter-rate DFE architecture with summer gain and power optimization; 3) an integrating summer with a compact common-mode restoration circuit. Leveraging these techniques, the DFE is capable of operating at or below 0.7V, with an energy efficiency of or better than 0.25pJ/bit.

Keywords

CMOS digital integrated circuits; decision feedback equalisers; flip-flops; 3-tap decision-feedback equalizer; CMOS-clocked quarter-rate DFE architecture; S-H topologies; bit rate 16 Gbit/s; charge-based latch; compact common-mode restoration circuit; energy-efficiency; power optimization; sample-and-hold topologies; size 65 nm; summer gain; voltage 0.7 V; Bit error rate; CMOS integrated circuits; Clocks; Decision feedback equalizers; Energy efficiency; Latches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4799-0918-6

Type

conf

DOI

10.1109/ISSCC.2014.6757331

Filename

6757331