MUSE: a wafer-scale systolic DSP

Author

Allen, David L. ; Anderson, Allan H. ; Rader, Charles M. ; Woodward, Charles

Author_Institution

MIT, Lincoln Lab., Lexington, MA, USA

fYear

1990

fDate

23-25 Jan 1990

Firstpage

27

Lastpage

35

Abstract

MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 μm CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4" by 4" silicon substrate

Keywords

CMOS integrated circuits; VLSI; cellular arrays; digital signal processing chips; radar equipment; special purpose computers; CMOS; MUSE; Matrix Update Systolic Experiment; real-time adaptive nulling; restructurable VLSI; rotator cell; space-based radar systems; special-purpose digital signal processor; wafer-scale integrated circuit; wafer-scale interconnect; wafer-scale systolic DSP; wafer-scale systolic array; Digital signal processing; Digital signal processors; Integrated circuit interconnections; Jamming; Real time systems; Silicon; Spaceborne radar; Systolic arrays; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on

Conference_Location

San Francisco, CA

Print_ISBN

0-8186-9013-5

Type

conf

DOI

10.1109/ICWSI.1990.63879

Filename

63879